CODEWITHSUNDEEP
chiselblack-box
NguyenDien
NguyenDien

Reputation: 31

How to generate code to RTL with blackbox?

When I want to convert code chisel to verilog with black box, I have error. How can I fix it?

[error] /data/workspace/chisel/chisel3-3.1.8/src/main/scala/tap/dti_bypass_register.scala:45:18: overloaded method value execute with alternatives:

import chisel3._
import chisel3.util._
  class dti_bypass_register extends BlackBox with HasBlackBoxResource {
  val io = IO(new Bundle {
    val clk_DR          = Input (Clock())// Bypass register clock
    val TDI             = Input (UInt(1.W))// data in
    val bypass_en       = Input (Bool())// enable signal
    val captureDR       = Input (Bool())// captureDR signal

    val TDO_bypass      = Output (UInt(1.W))// Serial data out
  })
    setResource("/dti_bypass_register.v")

}

object dti_bypass_registerDriver extends App {
  chisel3.Driver.execute(args, () => new dti_bypass_register)
}

Upvotes: 2

Views: 328

Answers (1)

Jack Koenig
Jack Koenig

Reputation: 6064

Chisel does not accept BlackBoxes as the top Module. Since BlackBoxes are simply interfaces that we emit a Verilog instantiation for, there's not really anything for Chisel to do with them.

Upvotes: 1

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