CODEWITHSUNDEEP
arraysvhdl
parafux
parafux

Reputation: 33

how can i specify a generic array of std_logic_vectors?

I have two generics of my module: A and B
I want to generate an input that is an array of std_logic_vectors with the following parameter:
number of array elements A
number of element width B

I want to create a type of that multidimensional array in a package with generic width in both dimensions.

is that correct:

TYPE t_pos1_in_vec IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(NATURAL RANGE <>);

Upvotes: 0

Views: 783

Answers (1)

Giampietro Seu
Giampietro Seu

Reputation: 816

In your package you have to write:

type t_pos1_in_vec is array (natural range <>) of std_logic_vector;

Note that there is no (natural range <>) after std_logic_vector.

Then in your entity:

entity my_entity is 
generic
(
    A : natural := 12;  -- number of elements
    B : natural := 32   -- element width
);
port (
    multidimensional_array : in t_pos1_in_vec(A-1 downto 0)(B-1 downto 0)
);
end entity my_entity;

Upvotes: 3

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