CODEWITHSUNDEEP
verilogxilinxspartan
FunkyLobster27
FunkyLobster27

Reputation: 41

Is it possible to switch between single ended and differential IO 'on the fly' (post configuration) in Xilinx Spartan-6 FPGA

I'm writing Verilog code for a Sparatn-6 Xilinx FPGA in which I would like to reconfigure IO during 'runtime' specifically, between single ended and differential IO buffers.

I have read through the list of IO buffer primitives in UG381.pdf but all seem to be fixed single ended or differential (on the pad side)

I have tried instantiating an OBUF and an OBUFDS but have found no way to mux the outputs of the bufs to a single pad, or combine them before or as part of their association with a pad. The wiring of adjacent pads to form differential outputs/inputs seems to be entirely hidden away, as you might expect, but also therefore seems to prevent the use of the OBUF for anything other than the differential function which it doesn't need to as such...

What envisage I need is:

SELECTABLE_SINGLE_DIFF_OBUFDS #(
   .IOSTANDARD ("LVDS_33")
) my_buf (
   .I       (my_signal),    // logic input (fabric side)
   .IO      (diff_p_out),   // Single ended o/p or Differential +ve (to pin)
   .IOB     (diff_n_out),   // Differential -ve (to pin)
   .MODE    (my_mode == 1)  // mode = 0, single ended output
                            // mode = 1, differential output
);

There must be something when you instantiate a OBUF or OBUFDS that configures the underlying SelectIO block's differential capabilities, I guess what I'm looking for is a way to access the underlying block from within Verilog so I can control the configuration of the IO Block from other logic in the FPGA.

Upvotes: 0

Views: 895

Answers (1)

Timmy Brolin
Timmy Brolin

Reputation: 1181

As long as you only need differential outputs, you can probably get away with just using two single-ended registered outputs and drive the negative output inverted.

Upvotes: 1

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