CODEWITHSUNDEEP
vhdlvunit
Marcus
Marcus

Reputation: 41

Is there a workaround for the data_width limitation (32 bit) in vunit_lib.array_pkg

I have the array_axis_vcs VUNIT example running. Now I want to customize the example to my needs, a.o. increasing the data_width size (32 bit in the example).

Doing this, the error below appears. It seems there is a limitation to 32 bit for the AXIS data width in the packages.

Is there a fundamental reason why this is? Maybe a workaround?

Actually I want to transmit 32 signed(9 downto 0) values per clock cycle, which I would then map to std_logic_vector(319 downto 0). I would expect the AXIS code just treat this payload as std_logic_vector, but somewhere it tries to convert it to signed.

# Stack trace result from 'tb' command
#  /usr/lib/python2.7/site-packages/vunit/vhdl/data_types/src/integer_array_pkg-body.vhd 220 return [address 0x7feff05dbae7] Subprogram set_word_size
# called from  /usr/lib/python2.7/site-packages/vunit/vhdl/data_types/src/integer_array_pkg-body.vhd 273 return [address 0x7feff05d8215] Subprogram new_3d
# called from  /usr/lib/python2.7/site-packages/vunit/vhdl/array/src/array_pkg.vhd 210 return [address 0x7feff0b9a75b] Subprogram array_t.init_3d
# called from  /usr/lib/python2.7/site-packages/vunit/vhdl/array/src/array_pkg.vhd 196 return [address 0x7feff0b9a642] Subprogram array_t.init_2d
# called from  /hsdtlvob/impala/design_sources/dpu_common/axis_buffer/src/test/tb_axis_loop.vhd 122 return [address 0x7feff0ba5ddb] Process save
# 
# 
# Surrounding code from 'see' command
#   215 :   procedure set_word_size(variable arr : inout integer_array_t;
#   216 :                           bit_width : natural := 32;
#   217 :                           is_signed : boolean := true) is
#   218 :   begin
#   219 :     assert (1 <= bit_width and bit_width < 32) or (bit_width = 32 and is_signed)
# ->220 :       report "Unsupported combination of bit_width and is_signed";
#   221 :     arr.bit_width := bit_width;
#   222 :     arr.is_signed := is_signed;
#   223 : 
#   224 :     if arr.is_signed then

Upvotes: 1

Views: 170

Answers (1)

lasplund
lasplund

Reputation: 1440

The problem you're experiencing is not related to the AXI Stream verification components but the array type used when reading/writing stimuli/result from/to file. The array type is based on 32-bit integers and can't handle larger vectors. To handle larger vectors you would have to use several integers in the CSV files for every stimuli/result vector, for example 2 integers for a 64-bit vector.

I also recommend that you use the newer integer_array_t instead of array_t. array_t is based on protected types which has a number of limitations which integer_array_t doesn't have. There is also work being done to support dynamic arrays of arbitrary type so that you can use your std_logic_vector(319 downto 0) directly or, maybe even better, create an array of arrays containing 32 signed(9 downto 0). Have a look at this issue for more information on that work.

Upvotes: 0

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