CODEWITHSUNDEEP
verilog
Kun Liu
Kun Liu

Reputation: 13

100-bit binary ripple carry adde

I am trying to write a 100-ripple carry adder. Fist I design a full adder. Then I need to connect 100 full adders. I am getting errors:

Error (10170): Verilog HDL syntax error at top_module.v(11) near text: "instance1"; expecting "<=", or "=", or "+=", or "-=", or "*=", or "/=", or "%=", or "&=", or "|=", or "^=", or "<<=", or ">>=", or "<<<=", or ">>>=", or "++", or "--". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /var/www/verilog/work/vlg7ccmQf_dir/top_module.v Line: 11

module top_module( 
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );

assign {cout[0],sum[0]}=a[0]+b[0]+cin;
always@ (*)
    begin
        for (int i=1; i<$bits(a);i++)
                full_adder instance1(
                    .a_1(a[i]),
                    .b_1(b[i]),
                    .cin_1(cout[i-1]),
                    .cout_1(cout[i]),
                    .sum_1(sum[i])
                );

   end
endmodule
module full_adder(
    input a_1, b_1,
    input cin_1,
    output cout_1,
    output sum_1
);
    assign {cout_1,sum_1}=cin_1+a_1+b_1;
endmodule

Upvotes: 1

Views: 1638

Answers (2)

Taher Anaya
Taher Anaya

Reputation: 105

You cannot instantiate a module inside of a procedural block. Try to use generate block instead:

The final code should be like this:

module top_module( 
  input [99:0] a, b,
  input cin,
  output [99:0] cout,
  output [99:0] sum
);
  assign {cout[0],sum[0]}=a[0]+b[0]+cin;
  genvar i;
  generate 
    for ( i = 1; i < $size(a); i++ ) begin : gen
      full_adder instance1(
        .a_1(a[i]),
        .b_1(b[i]),
        .cin_1(cout[i-1]),
        .cout_1(cout[i]),
        .sum_1(sum[i])
      );
    end : gen
  endgenerate
endmodule


module full_adder(
  input a_1, b_1,
  input cin_1,
  output cout_1,
  output sum_1
);
  assign {cout_1,sum_1}=cin_1+a_1+b_1;
endmodule

Please pay attention to the for-label ":gen", it is necessary and the code will not work without it.

Upvotes: 0

Serge
Serge

Reputation: 12384

well, you cannot instantiate a module inside of an always block. Try a generate block instead:

...
assign {cout[0],sum[0]}=a[0]+b[0]+cin;

genvar i;

for ( i=1; i<$bits(a);i=i+1)
  full_adder instance1(
    .a_1(a[i]),
    .b_1(b[i]),
    .cin_1(cout[i-1]),
    .cout_1(cout[i]),
    .sum_1(sum[i])
  );
...

Upvotes: 3

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