CODEWITHSUNDEEP
vhdl
Buğra Tufan
Buğra Tufan

Reputation: 33

Comparison two signed signal

I want to compare two signals. But when I compile my code I get "Illegal concurrent statement" error. How can I compare two signals?

Library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.numeric_std.all;

entity compare is
end entity;

architecture RTL of compare is

  signal a : signed (7 downto 0);
  signal b : signed (7 downto 0);
  signal c : std_logic;

begin
  if a>b then
    c <= '1';
  end if;

end RTL;

Upvotes: 0

Views: 730

Answers (1)

mfro
mfro

Reputation: 3335

if.. then (the sequential conditional statement) is only valid within a process in VHDL.

If you want a concurrent statement, you can use a conditional signal assignment instead:

c <= '1' when a > b else '0';

Upvotes: 1

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