CODEWITHSUNDEEP
veriloginterruptriscv
developer123
developer123

Reputation: 91

RISC-V exceptions vs interrupts

I am about to write my own RV32I core with a CLINT. However there is something which is not fully clear to me. At least I could not find it in the docs. Here is what the privileged isa spec says for ecall/ebreak:

ECALL and EBREAK cause the receiving privilege mode’s epc register to be set to the address of the ECALL or EBREAK instruction itself, not the address of the following instruction.

So this means, that setting the right mepc for mret is the responsibility of the SW handler. I assume that this behavior applies to all other exceptions too.

What about asynchronous interrupts? Does the HW set mepc to PC+4 automatically? From what I saw in different SW handlers it seems that it is like this, but I actually could not find it in the docs.

Hopefully someone can point me to the right documentation.

Upvotes: 4

Views: 5419

Answers (1)

Jörg Mische
Jörg Mische

Reputation: 131

Section 1.6 of the unprivileged RISC-V specification defines that exceptions are raised by instructions and interrupts are raised by external events.

When an (synchronous) exception is raised, the triggering instruction cannot be completed properly. Hence, there are two possibilities for the return address: either the instruction itself or the following instruction. Both solutions make sense. If it points to the instruction itself it is easier to determine the problem and react accordingly. If it points to the next instruction, the address need not be incremented when returning from the exception handler

(Asynchronous) interrupts are different, they break the stream of executed instructions of an independent thread. Therefore, there is only one reasonable solution for the return address: the first instruction that has not completed yet. Thus, when returning from the interrupt handler, the execution continues exactly where it was interrupted.

With this background, the brief definition in section 3.1.15 of the privileged RISC-V specification

When a trap is taken into M-mode, mepc is written with the virtual address of the instruction that was interrupted or that encountered the exception.

is clear: mepc points to the first uncompleted instruction, when an interrupt is raised or to the instruction that raised an exception.

Upvotes: 9

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