CODEWITHSUNDEEP
system-verilogvivado
Can Kırşallıoba
Can Kırşallıoba

Reputation: 37

Vivado Clock Implementation error SystemVerilog

I get the following implementation error. I have not clocks in my design. How can I fix this?

Implementation Place Design [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets en_IBUF] >

en_IBUF_inst (IBUF.O) is locked to IOB_X0Y11
 and en_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

[Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

Upvotes: 0

Views: 2684

Answers (1)

gatecat
gatecat

Reputation: 1186

It looks like you are attempting to use a non-global-clock-capable pin as a clock inside your design. I am not sure what you mean by "I have not clocks in my design", do note that even if your design is asynchronous I believe Vivado will use clock resources for latch enables - or it is possible that you do have clocks (this will be any always @(posedge ...) for example) and don't realise it.

Either you need to use a clock capable pin for the clock input; or accept possible issues such as duty cycle distortion from using non-clock-capable routing and suppress the error using the suggested "set_property" command in your xdc file.

Upvotes: 0

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