Use Vivado tool with create_clock and create_generate_clock

Question

first I want to know why create_clock, create_generate_clock, input delay, output delay. I already use clock in my Verilog code but when I run synthesis and implementation I can't get summary for timing. I researched Google, they said create_clock, create_generate_clock, input delay, output delay is important.

I can't understand about setting the constraints. Please teach me. Here is my Verilog code I used this code hierarchy. This code is 2by2 multiplier

////// full_adder //////
`timescale 1ns / 1ns

module full_adder(A, B, C_in, C_out, S );

input A,B,C_in;

output S,C_out;

wire line1;

wire line2;

wire line3;

wire line4;

wire line5;

assign line1 = A^B,
line2 = line1 ^ C_in,
line3 = line1 & C_in, 
line4 = A & B,
line5 = line3 | line4;

assign S = line2;

assign C_out = line5;

endmodule

/////// three_input_FA//////
`timescale 1ns / 1ns

module three_input_FA(a,b,v,h,
s_in,
s_out, c_in, c_out );


input a, b, v, h, s_in, c_in;

output s_out, c_out;

wire vh;

wire vhab;

assign vh = v ^ h;
assign vhab = vh & a & b;

full_adder inst1(s_in, vhab, c_in, c_out, s_out);

endmodule

////// useful_2by2 ///// 
`timescale 1ns / 1ps


module useful_2by2(
a,b,v,h,s_out,c_out
);

input [1:0] a;
input [1:0] b;
input [1:0] v;
input [1:0] h;

wire [2:0] s_in;

output [2:0] s_out;

wire [1:0] c_in;

output [1:0] c_out;

wire [2:0]s0_in;

wire [3:0]s0_out;

wire [1:0]c0_in;

wire [3:0]c0_out;

three_input_FA inst1(a[0],b[0], v[0],h[0], s0_in[0], s0_out[0], c0_in[0],  
c0_out[0]); 

three_input_FA inst2(a[1],b[0], v[1],h[0], s0_in[1], s0_out[1], c0_out[0], 
c0_out[1]); 
three_input_FA inst3(a[0],b[1], v[0],h[1], s0_out[1],s0_out[2], c0_in[1],  
c0_out[2]);

three_input_FA inst4(a[1],b[1], v[1],h[1], s0_in[2], s0_out[3], c0_out[2], 
c0_out[3]);

assign s_in[0] = 0, s_in[1] = 0, s_in[2] = 0,
    c_in[0] = 0, c_in[1] = 0;

assign c_out[0] = c0_out[1], c_out[1] = c0_out[3];

assign s_out[0] = s0_out[0], s_out[1] = s0_out[2], s_out[2] = s0_out[3];

assign c0_in[0] = c_in[0] , c0_in[1] = c_in[1];

assign s0_in[0] = s_in[0], s0_in[1] = s_in[1], s0_in[2] = s_in[2];

endmodule

`timescale 1ns / 1ps

//////// top_2by2//////
module top_2by2(
a,b,v,h,p,clk
);

input [1:0] a;

input [1:0] b;

input [1:0] v;

input [1:0] h;

input clk;

output reg [3:0]p;

wire  [3:0] s;

wire [2:0] s_in;

wire [2:0] s_out;

wire [1:0] c_in;

wire [1:0] c_out;

useful_2by2 inst1(a,b,v,h,s_out,c_out);

assign s[0] = s_out[0],   s[1] = s_out[1],   s[2] = s_out[2],   s[3] = 
c_out[1];

always @ (posedge clk)
p = s;
endmodule

Answer 1

In your code, you need to use create_clock to tell Vivado how fast your clk is.

You don't have any generated clocks so you do not need to use create_generated_clocks. If you use Xilinx clocking resources such as MMCM, Vivado derives the constraints for the generated clocks automatically so you still do not need to use create_generated_clocks.

Answer 2

Constraints are required by Vivado to ensure that timing is not violated from signals that are external to the top-level module, e.g. a clock signal. The tool ensures that internal signals will not violate hold/setup timing, but needs to know the clock speed to so, which is why it is required to generate a clock in the constraints. Furthermore, your inputs a, b, v, h, may drive logic in the FPGA, but Vivado has no way of knowing when they might change, i.e. whether they are synchronous or asynchronous to a clock, and the delay they may have from a clock edge. By specifying what delays your inputs have, Vivado can ensure that timing is still met. Lastly, Vivado needs to know the maximum delay of your output, p, to ensure that the signal won't violate any timing for external devices.

See https://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug903-vivado-using-constraints.pdf for more information on using constraints.