CODEWITHSUNDEEP
fpgafifovivado
OM222O
OM222O

Reputation: 1006

Dual clock FIFO in vivado (verilog)

I want to use a FIFO in a project where a state machine buffers as much data as possible to a FIFO, which will then be processed by a DSP block. To maximize data throughput I want to use multiple QSPI nor flash modules as a ROM with a wide data bus. DSP blocks can perform 1 operation per cycle which means the data input width has to be larger than the output width (because it takes 8 clock cycles to transfer data). For example, I want a FIFO with 32-bit input and 8-bit output, but this is not supported in vivado as far as I can tell. I tried the various FIFO block generators and even tried using the macros but I'm not having much luck.

Please let me know how I can generate a dual clock FIFO with a larger input width than the output width.

Upvotes: 0

Views: 1065

Answers (1)

mohammadhgh
mohammadhgh

Reputation: 59

Using FIFO Generator IP core in Vivado, choose Independent Clocks Block RAM for FIFO Implementation and then you will be able to set larger data width for write port than the read port.

enter image description here

enter image description here

Upvotes: 1

Related Questions