CODEWITHSUNDEEP
fpgavivado
pico
pico

Reputation: 1910

Vivado: TCL command to set timing paths between clock1 and clock2 as false path (TIMING-6 and TIMING-7)

Let's assume I have a FPGA/VHDL design that has two clock domains, and every path between one clock domain to anther clock domain has CDC synchronization code written in VHDL to make sure there are no meta-stability when passing information between crossing clock boundaries.

In this case, what's the Vivado TCL command to set the timing path between clock1 and clock2 to be a false path for every timing path between clock1 and clock2?

Example Compiler warning:

WARNING: [TIMING-6] The clocks clk_1 and clk_2 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_fpga_0] -to [get_clocks clk_out1_design_zynq_zyboz720_clk_wiz_0_0] 

WARNING: [TIMING-7] The clocks clk_1 and clk_2 are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_1] -to [get_clocks clk_2]

Upvotes: 0

Views: 2249

Answers (1)

Gautitho
Gautitho

Reputation: 623

set_false_path -from [get_clocks clk_1] -to [get_clocks clk_2]

This command will remove your warnings and the prospective critical warnings "Timing not met" related to this CDC but this will not ensure your design will work properly.

I advice you to also add the attribute ASYNC_REG on your resync signals to ensure that the synthetizer will place the 2 CDC FF very close (if possible in the same slice) :

attribute ASYNC_REG : string;
attribute ASYNC_REG of a_r_clk_2  : signal is "TRUE"; -- Output of the first resync FF in clk_2
attribute ASYNC_REG of a_rr_clk_2 : signal is "TRUE"; -- Output of the second resync FF in clk_2

Upvotes: 4

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