CODEWITHSUNDEEP
chisel
Hoohoo
Hoohoo

Reputation: 451

How to add include path of verilog to blackbox in chisel (3.2)

Sometimes it is needed to wrap other's verilog module to blackbox, The module may instantiates a lot of other modules, so it seems better to include a path to blackbox,

I saw there is an addPath method in HasBlackBoxPath trait which is not in the official guide.

But I'm not getting this include behavior. If do this:

class xxx extends BlackBox with HasBlackBoxResource with HasBlackBoxPath{
 val io = IO(new Bundle{
 ...
 })
 addResource("/xxx.v")
 addPath("/xxxx/xxx.../src/main/resources/Sim/")
}

It reports: Exception in thread "main" firrtl.transforms.BlackBoxNotFoundException: BlackBox '/xxxx/xxx.../src/main/resources/Sim' not found. Did you misspell it? Is it in src/{main,test}/resources?

Sim is the folder where .v files are in.

Currently I'm just using addResource() multiple times to add resources needed, but this way I have to look into the verilog code to find out what module are used and where to find.

I tried addResource("/path/*.v") without any luck.

Is there a way to include a batch of verilog, or include a path ?

Upvotes: 3

Views: 466

Answers (1)

Chick Markley
Chick Markley

Reputation: 4051

I think you should try only using one or the other, they do not combine. So something like

class xxx extends BlackBox with HasBlackBoxPath {
  val io = IO(new Bundle{
    ...
  })
addPath("/xxxx/xxx.../src/main/resources/Sim/xxx.v")

}

There are example usages in chisel3 /src/test/scala/chiselTests/BlackBoxImpl.scala

Upvotes: 1

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