CODEWITHSUNDEEP
c++ccode-reuseverilogsystem-verilog
Nathan Fellman
Nathan Fellman

Reputation: 127578

Is it possible to compile System Verilog functions to C or C++?

I work on a high-level simulator written in C++ for some hardware that is written in System Verilog.

The System Verilog code includes a number of functions that contain only logic (that is, nothing time-consuming, no flip-flops). I want to reuse this code in my C++ simulator.

Is there any way to reuse these functions in C++ (or C, which is easily linked into C++) by way of:

Upvotes: 4

Views: 8041

Answers (5)

user4398021
user4398021

Reputation: 7

Regarding verilator and DPI you may want to take a look at how I evaluated it:

"... In order to practice cpp (c++) verification benches, with system verilog DPI, using a verilog DUT, I decided to download verilator and do some self study exercises.

First I installed the software. This is fairly simple on a debian machine: apt-get install verilator..." http://bknpk.ddns.net/my_web/SystemC_MyFirst/verilator_my_first.html

Upvotes: 0

Jie Xu
Jie Xu

Reputation: 19

Verilator is a great tool for your purpose. Basically Verilator can compile your design to a C++ class which is a representation of the your top-level module. Then you can simulate the design by driving and stimulating the C++ class in your custom C++ code.

Verilator also support DPI interfaces, which means you can export Verilog function/task to C++ functions and import C++ function to be used in Verilog code.

Upvotes: 0

Andy
Andy

Reputation: 4866

Typically this kind of integration is done in the other direction, meaning calling C/C++ routines from Verilog. Of course, that only makes sense for verification components, obviously that can't be synthesized. The most likely environment to do what you want is a SystemC/Verilog cosimulation, but that implies both the use of a Verilog simulator (which you explicitly don't want), and a C model using SystemC.

Simulators seeking high performance often generate C or native code. I'm not aware of any way to extract specific functions from the generated code in VCS (the simulator I'm most familiar with), but it might be possible to do so with one of the open source simulators. Any commercial (i.e., licensed) simulator is unlikely to support generating code that you can run without a license. I'm not sure if your desire to use the Verilog functions independent of the simulator is driven by licensing, runtime overhead, tool installation burden, or something else entirely.

I'm assuming you don't maintain the SystemVerilog routines, so it may not be possible to change the way they're implemented. However, if it is possible, one common strategy when functionality is needed both in C and in Verilog is to write code generators that can transform a single definition into C and Verilog implementations.

Another more esoteric possibility is SystemC synthesis. It is relatively new and I don't have experience with it, but if you have access to the tools and they work for your functions, it would allow you to reuse a C implementation for C models, hardware simulation, and synthesis.

Upvotes: 3

Srinivasan
Srinivasan

Reputation: 11

If you have an underlying SV/Verilog simulator (such as free ones à la Icarus/CVC) then you could use DPI. Else one could try Verilator - I guess it is more of Verilog/V2K than SV, maybe you can map your SV code to Verilog?

Upvotes: 1

Rudi
Rudi

Reputation: 19940

A quick search brought Verilog2C++ and Verilator. I haven't used these programs; you need to try them yourself.

Upvotes: 2

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