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vhdlcase-insensitive
Cindy
Cindy

Reputation: 183

VHDL case insensitivity

I have seen capital letters of VHDL key words being used, probably for the coding style reason, such as IF - THEN - ELEIF - ELSE - END IF; LIBRARY IEEE; USE numeric_std.ALL; However, it says VHDL "language is , for the most part, NOT case sensitive". Therefore, I would assume that all the key words listed above could be written using small case letters as well.

Does anybody have a good knowledge on the few exceptions that the key words need to be (or have to be) in capital letters?

Upvotes: 4

Views: 2855

Answers (1)

Matthew
Matthew

Reputation: 13957

As far as I know the only things in VHDL that are case-sensitive are literals (fixed values in your code) of type character and string. So, for example, the std_logic type is an enumeration type of characters. With any character an upper-case letter is different to a lower-case letter. So, for example, 'X' and 'x' are different characters. So, if you are assigning an 'X' to something of type std_logic, for example, then you must use an upper-case 'X' not a lower-case 'x', because that is how the std_logic type is defined. eg:

my_signal <= 'X';

is OK but

my_signal <= 'x';

is not, because 'x' is not a valid std_logic value.

So, basically, VHDL is not case sensitive. It just seems like it might be when you are dealing with characters (and strings, which are just arrays of characters). Any language that could not distinguish between a lower-case and an upper-case letter would be a strange one indeed.

Upvotes: 6

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