CODEWITHSUNDEEP
makefilegnu-make
HerpDerpington
HerpDerpington

Reputation: 4473

Gnu make: Target in macro from subst

I want to generate a list of equivalent targets:

TARGETLIST = a b c d e f 

define RULE
$(subst X,$(1),file_X.txt) $(subst X,$(1),otherfile_X.txt) &: # some dependency
    # some commands
endef

$(foreach _t, $(TARGETLIST), $(eval $(call RULE, $(_t))))

This does not do what I want: If I want to build file_b.txt for example the recipe is not found. How do I fix this?

Upvotes: 1

Views: 559

Answers (1)

Renaud Pacalet
Renaud Pacalet

Reputation: 29280

Your problem comes from the double expansion that takes place in your macro when calling foreach-eval-call. You need to double the $ of your $(subst...: $$(subst.... But why not simply letting call do your substitutions?

TARGETLIST = a b c d e f 

define RULE
file_$(1).txt otherfile_$(1).txt &: # some dependency
    # some commands
endef
$(foreach _t,$(TARGETLIST),$(eval $(call RULE,$(_t))))

call automatically replaces the $(1) occurrences in the RULE macro by the current $(_t) of the foreach loop. This is what call is made for.

Upvotes: 2

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