CODEWITHSUNDEEP
verilog
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Reputation: 191

Modeling a (2^n) x m single port RAM

I am modeling a (2^n) x m single port ram using Verilog. This ram has an input enable port, input read-write port (rw) where when it is 1 then we will write into the ram and when it is zero we will just read, input address port (addr), inout data port and an input write_data port.

Here is the design code :

module single_port_ram # ( parameter n=4,m=4) (rw,addr,data,enable);
  input rw,enable;
  inout [m-1:0]data;
  input [n-1:0] addr;
  reg [m-1:0] ram [(2**n)-1:0]; 
  reg [m-1:0]data_reg;
  assign data = (enable & !rw ) ? data_reg : {(m-1){1'bz}};
  
  always @ (*) begin
   
    if(enable) begin
      if(rw) 
        ram[addr]<=data;// wrtite to the ram address
        else
          data_reg <= ram[addr] ; // read from ram address
    end
  end
endmodule

Here is the the testbench code :

module t_b # ( parameter n=4 , m=4);
  reg rw,enable;
  reg [n-1:0] addr;
  // Variables needed for the read and write strategy to/from the bi-directional port
 
  wire [m-1:0]data;
  reg  [m-1:0]write_data; // input data to be written
 
  
  assign data = (enable & rw) ? write_data: {(m-1){1'bz}};
 
  
  
  single_port_ram  tb (.rw(rw),.enable(enable),.addr(addr),.data(data));
                     
   initial begin 
    $dumpfile("dump.vcd");
    $dumpvars;
    end 
                     
initial begin
      // write
       enable=1; rw=1 ; #20
      addr=1; write_data='b 1 ;  #20
  
  // write again
       enable=1; rw=1 ; #20
      addr=2; write_data='b0 ;  #20
      
      // read
      
       
      rw=0 ;  addr=1;  #10
      
      
      
      
      
      $finish;
       end
                     
  endmodule

The problem is the ram should output z values in its data bidirectional port when we are writing and should output the desired values in the data bidirectional port when we are reading. This is not the case in my code. If you simulate it, you will find that the data port will follow the value of the write_data port when we are writing. What is the cause of this problem? I think it is in the tb code.

Upvotes: 2

Views: 348

Answers (1)

toolic
toolic

Reputation: 62037

In your testbench, you are currently always setting enable=1, and this never allows you to see z on the data. If you set enable=0, you will see z on your data. For example:

  // read
  rw=0 ;  addr=1;  #10

  // read
  enable=0; rw=0 ;  addr=1;  #10

  $finish;

Also, you have an error in the bit width of the z constant. Change:

{(m-1){1'bz}}

to:

{m{1'bz}}

Upvotes: 1

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