CODEWITHSUNDEEP
system-verilog
chandrashekhar goudar
chandrashekhar goudar

Reputation: 9

System verilog constraint for uniform address pattern

I want to add a constraint on "rand bit [7:0] addr[10]" such that we have address generated in uniformly increasing order from 0th index to 5th and uniformly decreasing order from 6th to last index. I am new to SV constraints, can someone help with ways to do this.

Upvotes: 0

Views: 624

Answers (1)

dave_59
dave_59

Reputation: 42748

class A;
  rand bit [7:0] addr[10];
  rand int step; // this needs to be an int to catch underflow/overflow
  constraint uniform {
     foreach (addr[index]) {
        index inside {[0:4]} -> addr[index] + step == addr[index+1];
        index inside {[6:8]} -> addr[index] - step == addr[index+1];
     }
     step inside {[1:25]};
  }
endclass

Upvotes: 0

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