CODEWITHSUNDEEP
assemblymipscpu-architecturecpu-hazard
richbai90
richbai90

Reputation: 5204

Data hazards in a single instruction

Considering the following mips code snippet

add $t1, $t1,$t2
lw $t1, 0($sp)

I understand that there is a WAW data hazard on $t1 between instructions 1 and 2, but is there a WAR hazard on line 1 because we read from and write to $t1 in a single instruction?

Upvotes: 0

Views: 216

Answers (1)

Erik Eidt
Erik Eidt

Reputation: 26646

We consider WAR hazard as a problem of out of order machine, due to executing instructions in other than program order.

Given the program

add $t4, $t1, $t5 ; instruction 1, program order
add $t5, $t1, $t2 ; instruction 2, program order

An out of order machine could decide to execute 1&2 in parallel, or even 2 first then 1, as there is no data dependency between them (no RAW).  This creates the opportunity for the WAR hazard — that if instruction 2 completes far earlier than instruction 1, without mitigation, instruction 1 would incorrectly see instruction 2's $t5 value — let's note that this new value is a real program value for that register (just that it is not valid for prior instructions) so, this makes 2 different possible values for $t5.

is there a WAR hazard on line 1 because we read from and write to $t1 in a single instruction?

No, within a single instruction, like add $t1, $t1, $t2 the processor does not have a new value of $t1 until it computes the result of the addition, for which it must have already sourced $t1 and $t2 — thus, there is no realistic possibility to confuse the new value with the old value (within an instruction) since the new value doesn't yet exist at the time of the addition.  There is no alternate ordering that will make the new value exist prior to the moment of the actual addition.

Upvotes: 2

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