CODEWITHSUNDEEP
vhdlmodelsim
Noah Thompson
Noah Thompson

Reputation: 33

VHDL "expecting type ieee.std_logic_1164.STD_LOGIC_VECTOR" when that is the type I'm giving

library IEEE;

use work.vec9Arr.all; 
use IEEE.STD_LOGIC_1164.all;

entity vector_scalar_multiplier is
port(
    in_a : in vec9arr;
    in_b : in std_logic_vector(15 downto 0);
    out_vec : out vec9arr);
end vector_scalar_multiplier;

architecture structure of vector_adder is

component multiplier is
    generic (
        O_width : integer := 8;
        P_width : integer := 8
    );

    port (
        in_O : in std_logic_vector(O_width - 1 downto 0);
        in_P : in std_logic_vector(P_width - 1 downto 0);
        out_F : out std_logic_vector((O_width + P_width) - 1 downto 0)
    );
end component;



begin


GEN_MULT : for i in 0 to 8 generate
MULT : multiplier
    generic map(O_width => 16, P_width => 8)
    port map(
        in_O => in_b,
        in_P => in_a(i),
        out_F => out_vec(i));
end generate;

end structure;

A pretty simple entity that multiplies every element of a vector by a scalar. I get the following error upon compiling:

enter image description here

I've been looking for some syntax error that might cause this, but I must be missing something. What might cause an error like this?

I don't think this is cause by the custom vec9arr as I have another VHDL file in the same directory that also uses vec9arr and doesn't have any issues.

Upvotes: 1

Views: 1886

Answers (1)

Lenna
Lenna

Reputation: 1280

Your entity name is: vector_scalar_multiplier
But your architecture declaration is: vector_adder

Therefore the signals you are referencing in your architecture can only be the signals that are defined in the vector_adder entity declaration and any internal signals you define with the signal keyword (Of which I see none of in this example)

Did you intend to define an architecture for vector_scalar_multiplier? If not could you please include the entity declaration for vector_adder?

Upvotes: 2

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