CODEWITHSUNDEEP
cmakefile
adersat
adersat

Reputation: 41

Make file, separate compilation failed

i try to do a Make file, (separate compilation), but the compiler gives me this error

here is the error:

make: *** No rule to make target 'stringFunction.o', needed by 'stringsmake'.  Stop.

and here is my make.mak:

  # Dateiname: stringsmake.mak

stringsmake: stringFunction.o stringMain.o                                                  
        gcc -o stringsmake stringFunction.o stringMain.o

stringFunctions.o: stringFunctions.h stringFunctions.c                                                                           
        gcc -c stringFunctions.c

stringmain.o: stringFunctions.h Stringmain.c                                                             
        gcc -c Stringmain.c

Upvotes: 0

Views: 88

Answers (2)

Suvajit Patra
Suvajit Patra

Reputation: 190

The below Makefile should do the job. But change stringFunctions.c to stringFunction.c and Stringmain.c to stringMain.c.

BASE = stringsmake
CXX = gcc
LIBFLAGS=-lm

main: $(BASE)

%.o: %.cc
      $(CXX) -c -o$@ $<

$(BASE): stringFunctions.o stringMain.o
      $(CXX) -o $@ $^ $(LIBFLAGS)

stringFunctions.o: stringFunctions.h
stringMain.o: stringFunctions.h

Upvotes: 0

Some programmer dude
Some programmer dude

Reputation: 409136

You have a lot of mismatches between different filenames. Both in spelling but also with upper- and lower-cases.

I suggest you learn how to use implicit rules, automatic variables and "standard" variables to create simpler makefiles.

Perhaps something like this:

# Standard flag for C source compilations
# Add option for extra warnings
CFLAGS = -Wall

# The main target
mystring: Stringmain.o stringFunctions.o
    $(CC) -o $@ $^

That's it really. There are implicit rules to build object files from C source files using the CFLAGS variable.

The automatic variable $@ expands to the current target, and the variable $^ expands to all the prerequisites. So $(CC) -o $@ $^ will expand to $(CC) -o mystring Stringmain.o stringFunctions.o.

You can add explicit rules to list dependencies (like the header files) but omit any command. Then the implicit rules will be used for the generation of the object files.

Please take some time to study the manual of the make program you're using (for example GNU Make).

Upvotes: 1

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