CODEWITHSUNDEEP
cgccmakefile
Yusuf Selim KARATAS
Yusuf Selim KARATAS

Reputation: 115

Source and Include for MakeFile in C

I am taking a Coursera course and I am totally stuck in one of the project. Project demands us to create a makefile but I could not.

Here is my files and folders:

project
|---include
    |---CMSIS
        |---cmsis_gcc.h
        |---core_cm4.h
        |---core_cmFunc.h
        |---core_cmInstr.h
        |---ore_cmSimd.h
|------common
        |---memory.h
        |---platform.h
|------msp432
        |---cmsis_gcc.h
        |---msp_compatibility.h
        |---syste_msp432.h
|---src
        |---interr.c
        |---main.c
        |---memory.c
        |---str.h
        |---system_msp.h
|---makefile
|---msp432p401r.lds
|---sources.mk

Here is my sources.mk and makefile.

sources.mk

makefile

For now, I just want to check whether makefile succesfully find related source and include files but it does not.

I have checked several example makefiles and could not find where is the fault of mine? What I have got here is:

enter image description here

What I understand from error is it can not find related memory.h file. What can I do?

Any help will be appreciated.

Thanks.

Upvotes: 0

Views: 573

Answers (2)

Beta
Beta

Reputation: 99084

Make searches for prerequisites in the working directory. It doesn't know that you have memory.h somewhere else, and will not go looking for without instructions.

One way to solve this is with the vpath directive:

vpath %.h common

You can use the same trick when you run into problems finding other prerequisites:

vpath %h common CMSIS
vpath %.c src

That will get echo "HI" to work, but you will have more trouble with a real rule that actually uses the prerequisites. To take a contrived example:

memory.o: memory.c memory.h
    $(CC) -c $(CFLAGS) memory.c -o memory.o

This will fail because although Make can find the prerequisites, the compiler still doesn't know where they are.

We tell the compiler where memory.c is by referring it to the list of prerequisites:

memory.o: memory.c memory.h
    $(CC) -c $(CFLAGS) $< -o memory.o

($< means the first prerequisite; Make will provide the path.) We could use the same trick (with some effort) to tell the compiler where to search for the header file, but it's usually simpler to put that in by hand:

memory.o: memory.c memory.h
    $(CC) -c $(CFLAGS) -Icommon $< -o memory.o

Upvotes: 2

MadScientist
MadScientist

Reputation: 100781

It's important to understand that make and the compiler are two completely different programs, that do different things and work different ways. Make can run a compiler, but it can also do all sorts of other things: it could build documentation, or an entire website, or copy files, etc. Basically make is a general-purpose tool that can investigate when files are out of date and run any command you give it to make that file "up to date", whatever that may mean.

So, when you create a variable like INCLUDES = -I... that is setting a make variable to a flag that can tell the compiler where your header files are.

That means nothing to make.

Make sees this rule:

ysk: memory.h memory.c

and says "ok to build the file ysk I need to have memory.h and memory.c". It looks in the current directory and those files don't exist (because they are in src/memory.h and src/memory.c) so it fails.

You need to put the paths into your makefile, so make can find them.

Upvotes: 1

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