CODEWITHSUNDEEP
verilogsystem-verilog
Pragya Rathore
Pragya Rathore

Reputation: 15

SystemVerilog concatenation assignment is incorrect

I was reading about concatenation from this website. The program is as follows:

program main ;
bit [4:0] a;
reg b,c,d;
initial begin
b = 0;
c = 1;
d = 1;
a = {b,c,0,0,d};
{b,c,d} = 3'b111;
$display(" a %b b %b c %b d %b ",a,b,c,d);
end
endprogram

The result for this is:

a 00001 b 1 c 1 d 1

How is c getting the value of 0 in the result when assigned to a in concatenation, when it has been assigned as 1?

Upvotes: 1

Views: 535

Answers (2)

Greg
Greg

Reputation: 19122

In Verilog, if the bit width and base is not declared, it is assumed to be a 32-bit decimal. Therefore, 0 is synonymous with 32'd0.

You want a = {b,c,1'b0,1'b0,d};. Or you could make it 2 bits of zero with with a = {b,c,2'b0,d};

Upvotes: 3

dave_59
dave_59

Reputation: 42788

The literals 0 and 1 are unsized, but they actually are implicitly 32-bits. According to the 1800-2017 LRM, it's illegal to put an unsized numeric literal inside a concatenation because of this common mistake. The tool you are using is not catching this.

You should write this with explicitly sized literals

a = {b,c,1'b0,1'b0,d};

Upvotes: 1

Related Questions