Reputation: 764
I have a Makefile that compiles an .so
object. Now, there is a need to compile some .o
's in different object, and include them into the large .so
.
Here is my Makefile:
CC=gcc
FLAGS=-Wall
SOURCES=$(shell echo *.c)
OBJECTS = $(SOURCES:%.c=%.o)
OBJ_FLAGS=-c -fPIC
INCL_DIR=./include
UTILS_DIR=./utils/
INCLUDES=-I/usr/include -I$(INCL_DIR) -I$(UTILS_DIR)
TARGET=ap_pcie_lib.so
TARGET_FLAGS=-shared
all: clean build_utils build_obj build_target cleanup
clean:
@rm -rf *.o *.so build/
@sudo rm -f $(LIBPATH)$(TARGET)
build_utils:
make -C utils/ # I wish to use three .o files from here
build_obj: $(OBJECTS)
build_target: $(TARGET)
$(OBJECTS): %.o: %.c
$(CC) $(CFLAGS) $(INCLUDES) -DTIME=$(TIME) $(OBJ_FLAGS) -o $@ $<
$(TARGET):
$(CC) $(OBJECTS) $(TARGET_FLAGS) -o $(TARGET)
cleanup:
@rm -r *.o
So there are three *.o
files that get created in .utils/
, but I don't know how to include them in my current $(TARGET)
? I've tried to do this inside of $(TARGET)
rule, but it forbids me to change this variable inside of a rule.
OBJECTS += $(shell echo utils/*.o)
Upvotes: 1
Views: 70
Reputation: 5301
Add the objects as prerequisites to the TARGETS rule and use the automatic variable $^
to expand them in the recipe:
$(TARGET): $(OBJECTS)
$(CC) $(TARGET_FLAGS) -o $@ $^
# expands into something like "gcc -shared -o ap_pcie_lib.so ap_pcie_lib.o utils/a.o utils/b.o utils/c.o"
Upvotes: 1