Reading and writing the register bank at the same clock cycle in the pipeline. There will be a data hazard in this situation?

Question

I’m studying computer architecture through the book “Computer Organization and Design, The Hardware Software Interface ARM Edition by David A. Patterson and John L. Hennessy” and while I was reading the Chapter 4 (The Processor), I came across some information that seems contradictory or misleading to me, so I would like that someone could confirm that or, if I’m wrong, explain me what I’m missing. In the beginning of the chapter, the author explains some elements of the datapath and, specifically regarding the reading and writing of memories and the register bank, he made the statements below:

"FIGURE 4.3 Combinational logic, state elements, and the clock are closely related. In a synchronous digital system, the clock determines when elements with state will write values into internal storage. Any inputs to a state element must reach a stable value (that is, have reached a value from which they will not change until after the clock edge) before the active clock edge causes the state to be updated. All state elements in this chapter, including memory, are assumed positive edge-triggered; that is, they change on the rising clock edge."(Page 261)

"FIGURE 4.7 The two elements needed to implement R-format ALU operations are the register file and the ALU. [...] Remember that writes are edge-triggered, so that all the write inputs (i.e., the value to be written, the register number, and the write control signal) must be valid at the clock edge. Since writes to the register file are edge-triggered, our design can legally read and write the same register within a clock cycle: the read will get the value written in an earlier clock cycle, while the value written will be available to a read in a subsequent clock cycle. [...]"(Page 265)

Well, these statements are quite consistent for me and are in line with what I learned in my graduation. Later, however, when dealing about pipeline hazards, he made an assumption that I believe to contradict the chosen clocking methodology for the system:

"The last potential hazard can be resolved by the design of the register file hardware: What happens when a register is read and written in the same clock cycle? We assume that the write is in the first half of the clock cycle and the read is in the second half, so the read delivers what is written. As is the case for many implementations of register files, we have no data hazard in this case." (Page 316).

The statement above tell us that there will be no data hazard if an instruction tries to read a register content in the same clock cycle that this same register is updated by an earlier instruction, which means that the content read is the updated one. This contradicts the design of the Register File, as we were told in the beginning of the chapter (see Figure 4.7). When we try to read a register, we’re going to fetch the content written in an earlier clock cycle, not the updated one, so, for me, there will be a data hazard in this situation. Could anyone clarify these questions for me?

Sorry for any english mistakes and best regards!

Answer 1

On ARM, all memory accessing instructions are issued to one single pipeline.
In other words, two memory accessing instructions don't dual issue to start with. Don't worry.