CODEWITHSUNDEEP
chisel
james
james

Reputation: 35

Connecting Individual Modules - Chisel

Hello I have a question regarding how to connect and map the ports between two modules, I will describe only the inputs and ouputs while excluding the control logic for each. The first module is a simple register whose output is the input to second module which is a demultiplexer

class simpleRegister extends Module {
    val io = IO( new Bundle { 
    val enable = Input(UInt(1.W))
    val in    = Input(UInt(8.W))
    val out   = Output(UInt(8.W))
    })
}

class demultiplexer extends Module {
  val io = IO(new Bundle { 
    val datain = Input(UInt(8.W))
    val dataout1 = Output(UInt(8.W))
    val dataout2 = Output(UInt(8.W)) 
  })

I am not sure if i should what method to use when I read " Interfaces & Bulk Connections" on github

Upvotes: 1

Views: 503

Answers (1)

CV_Ruddha
CV_Ruddha

Reputation: 406

You need to construct a top module that calls both the modules and perform the construction. This is pretty straight forward.

Your top module will look like this

class Top extends Module{
    //You can expose a top level IO bundle if you will
    val smplReg = Module(new simpleRegister)
    val dmux = Module(new demultiplexer)
    //connection of interest here is
    dmux.io.datain := smplReg.io.out
    //Make other connections as necessary
}

Interfaces and Bulk connections are when two IO bundles have similar fields instead of connecting each input/ output to the corresponding input/output you connect the bundle as a whole. This is just a way of optimizing your code.

Upvotes: 1

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