CODEWITHSUNDEEP
verilogsystem-verilog
Wirlous
Wirlous

Reputation: 19

Create a int parameter from a loop variable

I am trying to get a code similar to this to work:

module testModule #(    parameter LEN = 4,
                        parameter logic [0:0] OPTION = 1'b0 )
(
    input               Clk,
    input     [LEN-1:0] DataIn,
    input     [LEN-1:0] Condition,
    output    [LEN-1:0] DataOut_1,
    output    [LEN-1:0] DataOut_2
);

    // CODE 1
    always_ff @(posedge Clk) begin
        for (int i = 0; i < LEN; i++) begin
            if (OPTION == 1'b0) begin
                if (Condition[0]) begin
                    DataOut_1[i] <= DataIn[i];
                end else begin
                    DataOut_1[i] <= 1'b0;
                end
            end else begin
                if (Condition[i]) begin
                    DataOut_1[i] <= DataIn[i];
                end else begin
                    DataOut_1[i] <= 1'b0;
                end
            end
        end
    end

    // CODE 2
    always_ff @(posedge Clk) begin
        for (int i = 0; i < LEN; i++) begin
            int select = (OPTION == 1'b0) ? 0 : i;
            if (Condition[select]) begin
                DataOut_2[i] <= DataIn[i];
            end else begin
                DataOut_2[i] <= 1'b0;
            end
        end
    end

endmodule

OPTION can be either 0 of 1.

I would like CODE 1 and 2 to do the same thing, and I am trying to simplify CODE 1.

DataOut_1 and DataOut_2 return the same value, but I get the following errors in CODE 2 in line int select = (OPTION == 1'b0) ? 0 : i;

Local static variable with initializer requires 'static' keyword

automatic variable illegal in static variable initializer

And I am not sure if there is a way to do it

Upvotes: 1

Views: 484

Answers (2)

dave_59
dave_59

Reputation: 42788

This code is illegal because you are not allowed to declare an implicitly static variable select with an initialization expression.

The reason for this restriction is exactly for the mistake you have made thinking that select will get initialized each time through the loop. Variables with static lifetimes only get initialized once at time zero, whereas variables with automatic lifetimes get initialized each time they enter the procedural block they are declared in.

Verilog declarations inside procedural block are implicitly static (exceptions are variables i declared as part of a for loop, and variables declared inside class methods, which are automatic.

There are a number of ways to fix this.

  1. Explictly declare select with an automatic lifetime so that it gets initialized each iteration of the for loop.
  2. Separate the declaration and initialization into a declaration and assignment statements. The assigment statement executes each iteration of the loop
  3. Get rid of the variable and embed it onto the other expressions. That is essentially what code 1 and another answers does.

Upvotes: 1

toolic
toolic

Reputation: 62236

You can simplify CODE 1 by using a ternary and bitwise operator instead of the for loop:

module testModule #(    parameter LEN = 4,
                        parameter logic [0:0] OPTION = 1'b0 )
(
    input                Clk,
    input      [LEN-1:0] DataIn,
    input      [LEN-1:0] Condition,
    output reg [LEN-1:0] DataOut_1
);
    always_ff @(posedge Clk) begin
        if (OPTION == 1'b0) begin
            DataOut_1 <= (Condition[0]) ? DataIn : '0;
        end else begin
            DataOut_1 <= DataIn & Condition;
        end
    end
endmodule

Upvotes: 1

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