CODEWITHSUNDEEP
verilogsystem-verilog
chao
chao

Reputation: 63

Verilog/SystemVerilog syntax how to use a parameter to indicate the bit streamlength when it is > 32 bits?

I have this few code lines in my Verilog/SystemVerilog,

parameter DATA_SZ=45;
reg [DATA_SZ-1:0] r_data;
initial r_data = 45'h1F_A4A3A2A1A0;
// How to replace it by 'initial r_data = (DATA_SZ)'h1F_A4A3A2A1A0;?

Now how can I make it more scalable by replace 45 by DATA_SZ? Looks like it fails the syntax. Could anybody suggest some good method? Thanks!

Upvotes: 0

Views: 1303

Answers (1)

dave_59
dave_59

Reputation: 42748

There is no need to do this. You can just write

initial r_data = 'h1F_A4A3A2A1A0;

And the literal will be implicitly 0 padded on the right before being assigned to r_data. If you want to be pedantic, you can write an explicit cast

initial r_data = DATA_SZ'('h1F_A4A3A2A1A0);

Upvotes: 0

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