Problem with using division operator in Quartus using VHDL

Question

We need to divide two integers using VHDL and run on FPGA. Below is the the code we wrote for integer addition and it compile in the Quartus but when we try to compile the division code it gave error as

"Error (10327): VHDL error at divider.vhd(25): can't determine definition of operator ""/"" -- found 0 possible definitions".

when we search through the internet we show there are many posts that says generally integer division in VHDL not carrying out. Can anybody give us some advise to solve this problem. Thanks in advance

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity divider is

port 
    (
    --clock, resetn :IN STD_LOGIC;
       
        a       : in  std_logic_vector (11 downto -4);
        b      : in  std_logic_vector (11 downto -4);
        Enable_FA: in std_logic;
        result  : out  std_logic_vector (23 downto -8)
    );

end entity;

architecture behaviour of divider is
begin
process(a,b,Enable_FA)
    begin
    if (Enable_FA='1') then
        result <= a / b;
    end if; 
end process;    
end behaviour;