CODEWITHSUNDEEP
vhdl
IknowGainz
IknowGainz

Reputation: 11

Vhdl compare a std_logic_vector

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity converter is
port(sign_mag : in std_logic_vector(3 downto 0);
        twos_com : out std_logic_vector(3 downto 0));
end;

architecture converter_arch of converter is

begin
if to_integer(signed(sign_mag)) > 0 then
        twos_com <= sign_mag;
else
        twos_com<= "0000";
end if;
end converter_arch;

i am getting the error illegal concurrent statement. Can't figure out a way to compare the msb of the vector. i also tried something like (if sign_mag(3) = 0), but i also get the same error message.

Upvotes: 1

Views: 1855

Answers (2)

am9417
am9417

Reputation: 1036

As stated in the comment, if-then-else is a sequential statement which must be inside a process (or a function or a procedure = subprogram). So you're missing the process block inside your architecture.

As you said, you could compare only the MSB only if sign_mag(3) = '0' like you suggested (note the single-quotes, because you're comparing std_logic types). This removes the need for using other packages from IEEE library except std_logic_1164.

architecture converter_arch of converter is

begin
  process(sign_mag)
  begin

    if sign_mag(3) = '0' then
        twos_com <= sign_mag;
    else
        twos_com <= "0000";
    end if;

  end process;

end converter_arch;

Another possibility to have conditionals in VHDL is to use a case statement (inside a process, too). However, the value of sign_mag(3) is being compared here, so you may not be able to express the condition like you could with an if-then-else structure.

case sign_mag(3) is
  when '0' =>
    twos_com <= sign_mag;
  when others =>
    twos_com <= "0000";
end case;

...or without a process the signal could be assigned with when--else structure with conditional signal assignment which is a concurrent statement:

twos_com <= sign_mag when sign_mag(3) = '0' else (others => '0');

Upvotes: 1

sunriax
sunriax

Reputation: 831

Maybe tis helps:

library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Converter is
  generic(
            num_length : integer := 4
         ); 
    port(
            number  : in std_logic_vector((num_length - 1) downto 0);
            result  : out std_logic_vector((num_length - 1) downto 0));
end Converter ;

architecture Beh of Converter is
    signal temp : std_logic_vector((num_length - 1) downto 0) := (others => '0');
 begin
    
    result <= temp;
    
    process(number) is
    begin
        if signed(number) > 0 then
            temp <= number;
        else
            temp <= (others => '0');
        end if;
    end process;
end Beh;

Actually I´m not able to approve the given code

Upvotes: 0

Related Questions