Yujie
Yujie

Reputation: 445

What is the difference in scheduling threads?

I am currently learning about simultaneous multi-threading, multi-core and multi-processor scheduling of threads. I checked some information, my understanding is:

If there is a processor that supports simultaneous multi-threading, it turns one physical core into two logical cores. There are two processes, P1 and P2.

  1. My understanding: In Linux, each process is composed of at least one thread? So scheduling is based on thread scheduling?

P1 and P2 are respectively scheduled to two logical cores. They operate independently. This is the first situation. If there is a process P3, it consists of two threads t1 and t2. Schedule t1 and t2 to different logical cores respectively. So what is the difference between scheduling two different processes to separate logical cores and scheduling different threads in the same process to logical cores?

  1. My understanding: The process is the smallest unit of the system to allocate resources, and threads share the resources of the process. Threads in a process share virtual memory, PCB, and can access the same data. Therefore, when scheduling different threads in a process and scheduling threads in different processes, there is no difference for the processor. The difference lies in the address translation of the page table and whether the cache can be shared. For a multi-core processor, the processor does not care whether the threads belong to the same process. The consistency of the data is guaranteed by MESI. The physical location of the data is guaranteed by the page table.

Is my understanding correct?

Upvotes: 1

Views: 463

Answers (1)

Peter Cordes
Peter Cordes

Reputation: 363980

Right, there's no difference. The kernel just schedules tasks; each user task refers to a page table (whether that's shared with any other task or not).

Each logical CPU core has its own page-table pointer (e.g. x86 CR3).

And yes, cache coherency is maintained by hardware. The Linux kernel's hand-rolled atomics (using volatile, and inline asm for RMWs and barriers) depend on that.

Upvotes: 2

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