CODEWITHSUNDEEP
verilogcounter
gana uvm
gana uvm

Reputation: 31

finiate state machine have the issue with the logic

How to achieve the output as 0,1,2,3,4,5,6,7,6,5,4,4,3,2,1 using Verilog counter FSM for up-down counter with repeat .the four should repeat two times here am using two states up down it's working fine for up down.

CODE

  module top(
            input clk,rst,
            output logic [2:0] dout
            );
            
        typedef enum {up,down} state_type;
        state_type state = up;
         
        integer count = 0;
         
        always@(posedge clk)
        begin
        if(rst == 1'b1) begin
        //dout <= 0;
        count <= 0;
        end
        else begin
        case(state)
        up:
        begin
        if(count == 7) begin
        count <= count - 1;
        state <= down;
        end
        else begin
        state <= up;
        count <= count - 1;
        end
        end
         
        down: begin
        if(count == 0) begin
        count <= count + 1;
        state <= up;
        end
        else begin
        state <= down;
        count <= count - 1;
        end
        end
         
        default: begin
        state <= up;
        count <= 0;
        end
        endcase
        end
        end
        assign dout = count;
         
        endmodule

Upvotes: 0

Views: 173

Answers (2)

Tinkerer
Tinkerer

Reputation: 1068

How about this?

module oddstep(
    input wire clk,
    input wire rst,
    output reg [2:0] step);

    reg dir;
    reg hold;

    always @(posedge clk)
      begin
        if (rst)
          begin
            step <= 3'b000;
            hold <= 1'b0;
            dir <= 1'b1;
          end
        else if (dir)
          begin
            step <= (step + 3'b001);
            if (step == 4)
              begin
                hold <= 1'b1;
              end
            else if (step == 6)
              begin
                dir <= 1'b0;
              end
          end
        else if (step != 1)
          begin
            if ((step == 4) & hold)
              begin
                hold <= 1'b0;
              end
            else
              begin
                step <= (step - 3'b001);
              end
          end
      end
endmodule /* oddstep */

Upvotes: 1

Rich Maes
Rich Maes

Reputation: 1222

Logically, you need to tell your machine about the condition of 4 on the Down count and you also need to make it know the difference between the first time or second time you have hit 4. The first time you want to stall and the second time you want to decrement. Currently you have the states up and down. So you might think about having up, down and downto4. Maybe you switch from up to downto4 when you reach 7, and then when you are decrementing, and hit 4 with a state of downto4, you keep the 4 count and then set state to down.

There are some other ways to think about this to. Imagine if you took a four bit counter and only looked at the upper 3 bits. Those 3 bits could still hold your 0 to 7 values that you are looking for. On UP and DOWN, if you add and subtract 2 from that counter, your upper three bits appear to increment by 1. Now imagined if you were in a state of 1010. The upper three bits look like binary 5. So if you now subtract 1 from the value you will get 1001. The upper three bits look like a binary 4. Subtract one more, and you get 1000. The upper three bits still look like 4. The cool thing here is logically you are always subtracting on the down count, but you might be able to say, if the value is 5 or 4, just subtract one on the next count. You will have to play around with the logic, but I think you get that to work too.

Upvotes: 1

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