CODEWITHSUNDEEP
mipscpu-architecture
user1286550
user1286550

Reputation: 101

Do all I-type instructions take the same number of cycles on a multi-cycle MIPS?

Do all I-type MIPS instructions take the same number of cycles in a multi-cycle datapath? I know R-type have the same number of cycles.

Upvotes: 1

Views: 991

Answers (1)

Erik Eidt
Erik Eidt

Reputation: 26656

Do all I-type MIPS instructions take the same number of cycles in a multi-cycle datapath?

No.

First, let's look at some of the instructions are included in the MIPS I-Type category: addi and lw.  These are both I-Type instructions — with the identical 16-bit immediate and rs and rt fields.  They are decoded using the same fields, which is why they are both considered I-Type instructions.

Ok, next, let's look at the multicycle processor.  This is not a pipelined processor, though, generally speaking, it will have a cycle for each stage in an equivalent pipelined version.

While we would generally find a pipelined processor's performance superior at the same megahertz, one advantage of a multicycle processor implementation over a pipelined processor implementation is that "stages" that are not needed can be skipped (skipping a cycle is not viable in a pipelined processor because of the instruction execution overlap; whereas the multicycle processor does not overlap execution of instructions).

So, among IF, ID, EX, MEM, WB stages, addi does not require or make use of the MEM stage, and thus it would be silly not to skip that cycle, making addi a 4 cycle instruction.

However, lw, does require the MEM stage (so all the stages) hence it will be 1 cycle longer than addi.

Upvotes: 1

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