CODEWITHSUNDEEP
system-veriloguvm
UVMag
UVMag

Reputation: 133

How to verify delays between signals using UVM?

I have a number of signals that I would like to verify the delay between them.

For example, lets define register with the name X_Y_DELAY which configure the time should pass from the rise of X signal to Y signal.

I want to make sure that the value I write to the X_Y_DELAY register is really the time between the signal increases.

I wonder if the right way is to do it through the uvm scoreboard or through the monitor while the signals arrive?

Thanks

Upvotes: 0

Views: 725

Answers (1)

Brian
Brian

Reputation: 710

This is really best done in an assertion within the interface itself.

Upvotes: 1

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