CODEWITHSUNDEEP
verilogyosys
张小禹
张小禹

Reputation: 11

convert verilog to aiger with Yosys

I have several verilog files which I want to convert to aiger format using Yosys, I use the following commmad in yosys:

read_verilog gclk_reg.v nld_and.v my_ff_W_8_.v gated_netlist.v

synth_xilinx -flatten -top gclk_reg

aigmap

write_aiger -ascii my.aag

When I use the aigmap command, it show that cells like:

VCC LUT2 GND LDCE

cannot be replaced.

Unsurprisingly, the write_aiger command fails, showing that:

"ERROR: Unsupported cell type: VCC (VCC)".

So how can I map those cells to allowed cells of write_aiger?(I also used the abc -g AND command but it still failed)

Many Thanks!!

Upvotes: 1

Views: 924

Answers (1)

gatecat
gatecat

Reputation: 1186

Use synth instead of synth_xilinx. This will map to a set of Yosys-internal gates that aigmap understands, rather than to a set of Xilinx primitives.

Upvotes: 1

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