CODEWITHSUNDEEP
system-verilog
shaymin shaymin
shaymin shaymin

Reputation: 197

Generate inside always_comb block in SystemVerilog

I know you can not have a generate inside an always_comb block in SystemVerilog, but I want to do something similar to what I show below and I do not know how I could do it.

genvar i, j;
generate
for (i = 0; i < 4; i++) begin
    always_comb begin 
        unique case (STATE) 
            0: begin
               ...
               for(j = 0; j < 8; j++)
                   var[j*8+2*i+1:j*8+2*i] = 2'b11;
            end
            ...
        endcase

    end
end
endgenerate

Right now it gives me the following compilation error : Unknown range in part select Any help would be apreciatted.

Upvotes: 0

Views: 3321

Answers (1)

Serge
Serge

Reputation: 12354

  1. var is a keyword in verilog, it cannot be used as a variable.
  2. genvar j cannot be modified inside an always block.
  3. partselect in system verilog must at least have a constant width.
  4. you missed endgenerate

so, you need to

  1. rename var to something else
  2. declare j as a non-genvar variable, i.e., int
  3. your width is always 2, so you can use the system verilog +: or -: range specifiers
  4. you do not really need generate..endgenerate markers any longer in system verilog.

here is an example:

genvar i;
//generate
  for (i = 0; i < 4; i++) begin: loop
    always_comb begin 
        unique case (STATE) 
            0: begin
               //...
              for(int j = 0; j < 8; j++)
                v[j*8+2*i +: 2] = 2'b11;
                   //v[j*8+2*i+1:j*8+2*i] = 2'b11;
            end
            //...
        endcase
    end
  end
//endgenerate

Upvotes: 2

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