CODEWITHSUNDEEP
verilogsystem-verilog
nillu
nillu

Reputation: 715

Is it allowed to instantiate a module inside always_comb block in system verilog?

Is it allowed to instantiate a module inside always_comb block in system verilog?

always_comb 
begin
   OR OR1 (.Y(A), .A(Z), 
end

Upvotes: 0

Views: 2479

Answers (1)

sharvil111
sharvil111

Reputation: 4381

First of all, your code is incomplete. Obviously, a two-input OR gate requires three connections.

In verilog, when you are instantiating a module, that means you are adding extra hardware to the board.

This hardware must be added before simulation starts(i.e. at compile time). Here, you can not add/remove hardware at each clock pulse.

Once instantiated, the module is executed/checked for each timestamp of simulation, till the end.

So to execute any module, just instantiate it, providing the required inputs to it (and add the always block in the sub-module itself, if necessary).

// Simply instantiate module
OR OR1 (.Y(A), .A(Z), .B(M));

Either way, you can add a combinational block to the current module itself:

// Directly use ORing
always_comb begin
  A = Z | M;
end

More information on instantiation can be obtained from Verilog Module Instantiation, Instantiating Modules and Primitives, Structural Modelling links.

Upvotes: 6

Related Questions