CODEWITHSUNDEEP
verilogsystem-veriloghdl
TheSprintingEngineer
TheSprintingEngineer

Reputation: 319

Why verilog "always_comb block contains only one event control" error flagged on always procedural block with multiple "@"

the following code below generates this error message:

"verilog always_comb imposes the restriction that it contains one and only one event control and no blocking timing controls"

always_comb begin
if (sig_a)begin
 @(posedge sig_b); // wait for a sig_b posedge event
 @(negedge sig_b); // then wait for a sig_b negedge event
 event_true=1;  
end

if (event_true)begin
  @((sig_c==1)&&(sig_a==0)); //wait for sig_a to deassert and sig_c assert event to be true
  yes =1;
 end
 else yes =0;

end

Why does the combi logic procedural block generate this error ?

And would an always block with @ event wait be synthesizable ?

Upvotes: 0

Views: 2072

Answers (2)

dave_59
dave_59

Reputation: 42698

The message reported by that error is misleading. You are not allowed ANY event controls in an always_comb block. It creates the event sensitivity list automatically for you. Maybe it is combining the implicit event control with the ones you added to it, then generating the error.

Unless you are using a high-level synthesis tool, you are restricted to having one event control at the beginning of a basic always block.

Upvotes: 2

Serge
Serge

Reputation: 12354

always_comb is for combinational logic only. the @ statements you use have nothing to do with combinational.

from lrm 9.2.2.2.2

Statements in an always_comb shall not include those that block, have blocking timing or event controls, or fork-join statements.

In your case you need to use a general purpose always. always @* will probably do.

Upvotes: 1

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