CODEWITHSUNDEEP
verilog
Mushtaq
Mushtaq

Reputation: 41

How to use two events in an "always" block in verilog

I have two push buttons (using Basys2 rev C board) and I want to increment a register (counter) when I push one of them. I used this:

always @( posedge pb1 or posedge pb2 )
 begin
 if(count2==9) count2=0;
 else count2= count2+1;
 end

but when I implemented it (using ISE 9.2), an error appeared:

The logic for does not match a known FF or Latch template.

However when I tried it using just one event (posedge pb1), it worked.

So why did that happen?

Upvotes: 4

Views: 3632

Answers (1)

FriendFX
FriendFX

Reputation: 3079

The error message means that the target technology (I am guessing in your case is an FPGA or CPLD) doesn't have the physical circuit required to implement the functionality you described with this behavioural code.

One of the important things to consider when writing synthesizable RTL (verilog or VHDL) is you are describing an electronic circuit. You should understand what real world logic you are trying implement (combinatorial logic, registers) before you start coding. In this case, you are describing a register with two separate clocks--something that doesn't exist in any FPGA or ASIC library I've seen. If you can't figure out what you're trying to implement, the chances are the synthesizer can't either.

In other words, not everything you can describe in Verilog can be translated into an actual circuit.

The solution depends on what you want to do - if you require that the counter increments on both pb1 and pb2 rising edges, irrespective of the other pbs state, I would look into solutions which use another (independent) clock (clk in the code below) - something like this:

reg old_pb1, old_pb2;
always @ (posedge clk) begin
  if (old_pb1 == 0 && pb1 == 1)
    if(count2==9) count2 = 0;
    else count2 <= count2 + 1;
  if (old_pb2 == 0 && pb2 == 1)
    if(count2==9) count2 = 0;
    else count2 <= count2 + 1;
  old_pb1 <= pb1;
  old_pb2 <= pb2;
end

If you have no other clock, you could also combine both input signals like in this example:

wire pbs = pb1 | pb2;
always @ (pbs) begin
 if(count2==9) count2 <= 0;
 else count2 <= count2 + 1;
end

Another option would be to use independent counters for the inputs:

always @ (posedge pb1)
 begin
   if(count_pb1==9) count_pb1 <= 0;
   else count_pb1 <= count_pb1 + 1;
 end
always @ (posedge pb2)
 begin
   if(count_pb2==9) count_pb2 <= 0;
   else count_pb2 <= count_pb2 + 1;
 end

wire [4:0] count2 = count_pb1 + count_pb2;

All options have their own restrictions, limitations and drawbacks, therefore it depends heavily on what you want to do. Corner cases matter.

Note that I put these example codes together without testing them - please let me know in a comment if you are having trouble with any of them and I look into it.

Upvotes: 1

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