CODEWITHSUNDEEP
verilog
BlueHorn07
BlueHorn07

Reputation: 41

Verilog: Can two always blocks be merged into one always block?

I have a Question that two always @(posedge clk) blocks would be identical to one always @(posedge clk) block.

For example,

always @(posedge clk) begin
    // do task1
end

always @(posedge clk) begin
   // do task2
end

is identical to this one?

always @(posedge clk) begin
    // do task1
    // do task2
end

Thank you

Upvotes: 1

Views: 1100

Answers (2)

Oldfart
Oldfart

Reputation: 6259

No, they are not.

In the first example the two tasks are executed in parallel. In the second they are executed sequentially.

Here is an extreme example where things not only are different but there is even a nasty side effect. So let's first define a clock and two tasks:

reg clk,a,b;

   initial
   begin
      clk = 1'b0;
      a = 1'b0;
      b = 1'b0;
      forever
         #50 clk = ~clk;
   end

task task1;
begin
   #10;
   a <= 1'b1;      
   #30;
   a <= 1'b0;
end
endtask


task task2;
begin
   #10;
   b <= 1'b1;      
   #70;
   b <= 1'b0;
end
endtask

Now if we call the tasks separately each finishes before the end of the clock cycle. 

always @(posedge clk) begin
    task1;
end

always @(posedge clk) begin
   task2;
end

This gives the following waveform in which the pattern repeats every clock cycle and the two waveform are in parallel:

enter image description here

I we use the second code, the total time in the task is longer then the clock cycle. 

always @(posedge clk) 
begin
   task1;
   task2;
end

This gives a different waveform in which the patterns are sequentially, but also repeats every second clock cycle.

enter image description here

Upvotes: 4

dave_59
dave_59

Reputation: 42698

It depends. If there are no dependancies between the two tasks, which normally there won't be for synthesizable RTL, then it does not matter.

But if there is a requirement that task1 executes before task2, then only the single always block can guarantee that.

Upvotes: 2

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