CODEWITHSUNDEEP
vhdl
Theodore Norvell
Theodore Norvell

Reputation: 16251

In VHDL how best to wait for a clock edge in a test bench

When writing test benches, is there any problem with writing

wait for 1 ns ; wait until rising_edge( clock ) ;

every time I want to wait for the next rising edge?

I'd like to put this sequence in a procedure and then always use it.

The reason I want to wait for 1 ns is that if I simply have the wait untils and there is no signal assignment in between two of them, they will collapse into one.

The clock cycle time is 10ns, so 1 ns shouldn't be a problem. What I'd really like to do is wait for one delta, but I don't know how to do that. Is it possible?

Are there hidden pitfalls to this approach?

We're using VHDL 93 with the ISIM simulator.

Upvotes: 1

Views: 3146

Answers (2)

Jim Lewis
Jim Lewis

Reputation: 3993

You don't need the wait for 1 ns.

One way to wait for 5 clocks is:

wait until rising_edge( clock ) ;
wait until rising_edge( clock ) ;
wait until rising_edge( clock ) ;
wait until rising_edge( clock ) ;
wait until rising_edge( clock ) ;

One simplified rule is that the wait statement always suspends the process for at least a simulation/delta cycle.

With a wait until that does not have an explicitly supplied on sensitivity-list (such as the example above), there is an implied on sensitivity-list that has every signal in the until clause in it. Hence, the above is equivalent to:

wait on clock until rising_edge( clock ) ; 
wait on clock until rising_edge( clock ) ; 
wait on clock until rising_edge( clock ) ; 
wait on clock until rising_edge( clock ) ; 
wait on clock until rising_edge( clock ) ;

Maybe this longer form is a little more obvious - when clock changes and rising_edge( clock ) is true the wait statement will resume and continue to the next wait statement. The next wait statement suspends until a change on clock occurs.

Upvotes: 7

Renaud Pacalet
Renaud Pacalet

Reputation: 29335

Your wait for 1 ns is useless. With or without it will not change anything as long as the clock period is larger than 1 ns and you execute this more than 1 ns before the next rising edge of the clock. To wait for a number of rising edges of the clock you could define a procedure in the declarative region of your architecture:

procedure waitNre(n: positive) is
begin
  for i in 1 to n loop
    wait until rising_edge(clk);
  end loop;
end procedure waitNre;

And then:

waitNre(5);

to wait for 5 rising edges of clk. If you want to share this among designs put the procedure's declaration/definition in a package and add the clock signal to the procedure's inputs:

procedure waitNre(signal clock: std_ulogic; n: positive) is
begin
  for i in 1 to n loop
    wait until rising_edge(clock);
  end loop;
end procedure waitNre;

And then:

waitNre(MyClk, 5);

As noted by Jim in a comment you could also declare the n parameter as an integer such that calling the procedure with a 0 or negative value would simply skip the loop (no wait). Or as a natural, if you know for sure that calling the procedure with a negative value indicates a coding error somewhere.

Upvotes: 2

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