CODEWITHSUNDEEP
system-verilog
Yike Wang
Yike Wang

Reputation: 23

How do I fix "Error: Illegal range in part select"?

bit[2:0]  size;
bit[2:0]  num;
bit[59:0] data;
data = 60'h12345;
num = 3'h1;
size = 3'h1;

data = {(num+1){data[(size+1)*10-1:0]}};

////Error-[IRIPS] Illegal range in part select

////Warning-[WUIMCM] Unknown in multiconcat multiplier

How do I fix these?

Upvotes: 1

Views: 6840

Answers (1)

dave_59
dave_59

Reputation: 42623

SystemVerilog does not allow variable widths in operands. You need to create a mask to select the part of the data variable, and need to use a for loop for replication.

bit [59:0] data_select = data;

data_select &= (61'b1 << (size+1)*10) - 1;
for(int i=0;i<num+1;i++) begin
   data <<= (size+1)*10;
   data |= data_select;
end

Upvotes: 1

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