CODEWITHSUNDEEP
system-veriloguvm
AVS Vaishnavi
AVS Vaishnavi

Reputation: 23

What is the purpose of a driver in UVM?

Since the generator generates test stimuli for the DUT (Design Under Test), why not feed them directly? What is the need for a driver? Please enlighten me with an example if possible.

Upvotes: 1

Views: 622

Answers (2)

dave_59
dave_59

Reputation: 42698

The UVM was developed using the Separation of Concerns principle in software programming. In Object Oriented Programming, this usually means giving a class one basic responsibility and passing data on to another class for another responsibility.

The UVM separates the job of generating stimulus from driving the signals into the DUT to enable re-use at different stages of abstraction because of different levels of unit testing. In the UVM, you will see that even the passing of data is abstracted into a separate set of classes called TLM ports and exports.

An example might be a design that processes an encrypted image received through a serial port. Your design will probably have stages the deserialized the serial input, decrypted the input, and finally stores an image in memory. Depending on which stage you are testing, you would want to use the same image generator and send the image through a sequence, and have layered sets of sequences to translate to the particular stage you are testing.

Upvotes: 0

toolic
toolic

Reputation: 62082

UVM is based on transaction-level modeling (TLM). This means that you can model things like memory reads and writes at a high level of abstraction using a transaction object. For example, a memory transaction can be represented by:

  • Data value
  • Address
  • Direction (read or write)

In UVM, we typically create a uvm_agent which consists of a sequencer, a driver and a monitor. The sequencer plays the role of the transaction generator. You will also create a sequence which is attached to the sequencer to generate several transactions. Each transaction object is sent from the sequencer to the driver.

When the driver receives a transaction object, it looks at the object properties and assigns the transaction values to the interface signals. In the testbench, the interface signals are connected directly to the DUT ports.

The driver contains more details than the sequencer or transaction. It controls the timing of the signals, adding delays, wait-states, etc.

See also chapter 1 of the UVM User's Guide

Upvotes: 2

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