CODEWITHSUNDEEP
verilogsystem-verilog
None
None

Reputation: 2433

How to parameterize verilog attribute (* *)?

How can I declare a signal with a verilog attribute depending on module's parameter?

I tried:

if (KEEP_VERILOG) begin
  (*keep="true"*)reg mysig;
end else begin
  reg mysig;
end

// doing something with mysig

I get a synthesis error: mysig is not declared

Upvotes: 0

Views: 1431

Answers (2)

Serge
Serge

Reputation: 12354

Attribute spec allows using constant expressions. Therefore you can use module parameter directly in the attribute:

(*keep=KEEP_VERILOG*) reg mysig;

The value of the attribute will have the value of the parameter.

Upvotes: 3

dave_59
dave_59

Reputation: 42673

You cannot reference a signal declared in an unnamed begin/end block from outside that block. Give the block a name (and you have to give both blocks the same name for what you want to do) and use that name in the reference.

if (KEEP_VERILOG) begin : blockname
    (*keep="true"*)reg mysig;
end else begin : blockname
  reg mysig;
end

// do something with blockname.mysig

Upvotes: 1

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