CODEWITHSUNDEEP
assembly64-bitmultiplicationriscvinstruction-set
adrianmcmenamin
adrianmcmenamin

Reputation: 1129

Behaviour of RISC-V mulh assembly instruction

The RISC-V reader states that mulh rd, rs1, rs2 "multiplies x[rs1] by x[rs2], treating the values as two'cplement numbers, and writes the upper half of the product to x[rd]"

So I am trying to multiply two signed 64 bit numbers and get a signed 128 bit result:

 mulh t0, a0, a1
 mul t1, a0, a1

And I'd expect that t0 would hold the upper 64 bits and t1 the lower 64 bits, but if a0= 0x7fffffffffffffff (ie MAX-INT) and a1 = 2, I get:

t0 = 0, t1=0xfffffffffffffffe as though I'd carried out an unsigned multiplication. And not t0 = 1 , t1= 0x7fffffffffffffff which appears to me to be the correct answer for two's complement arithmetic.

Now - in writing this out, I can see why I get t1=0xffffffffffffff, but I still don't get why I get t0=1, which would allow me to implement some logic to correct the sign bit in t1.

What have I got wrong here? I used to have rather complex bit-by-bit long multiplication algorithm for this, but this seemed so much simpler, but it (obviously) doesn't seem to work.

Upvotes: 0

Views: 1770

Answers (1)

Erik Eidt
Erik Eidt

Reputation: 26636

The 128-bit answer to 2 x 0x7FFFFFFFFFFFFFFF is

0x0000000000000000FFFFFFFFFFFFFFE
  |------ t0 ----||----- t1 ----|
  |
  |
  +-- the sign bit is the uppermost bit of this hex digit

Because you're multiplying two positive numbers, the answer is the same bit pattern whether you choose signed or unsigned multiplication.

Upvotes: 2

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