CODEWITHSUNDEEP
initializationsystem-verilog
Martel
Martel

Reputation: 2734

Initializing a memory block in SystemVerilog from outside a module

I have a SystemVerilog module like:

module my_mod(...);
   reg [31:0] mem [64];
   ...

I want to be able to instantiate that module with a particular set of initial values. So far, I do it with an initial block inside my_mod, but I want to be able to do it from outside, so different instances/tests of the module have different values. Something like:

my_mod #(.INITIAL_VALS(multi_dimensional_reg)) mm(...);

How can I do it?

Upvotes: 0

Views: 747

Answers (1)

dave_59
dave_59

Reputation: 42623

You can use a parameter to initialize a memory and then override instances as you need.

module my_mod #(
  logic [31:0] INITIAL_VALS[64] = '{0:0, 1:2, 3:4, 4:6, default:'x} )
  ();
  
   logic [31:0] mem [64];
   initial mem = INITIAL_VALS;
  
endmodule

module top;
  
  my_mod #(.INITIAL_VALS('{default:0}) ) m1();
endmodule

Note that you have to override all (64) elements of the array. You can use a function as well as a literal assignment pattern.

Upvotes: 1

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