CODEWITHSUNDEEP
vhdl
Doug Smith
Doug Smith

Reputation: 61

VHDL reset option in signal

Typically a clocked process can also have a reset trigger in sensitivity and can be used to initialize a value. However, it is my understanding that the following does the same.

signal  mc_var: unsigned(40 downto 0) := (others =>'0'); -- value gets reset here.

my_counter: process (CLK)
IF (rising_edge(CLK)) THEN
     mc_var <= mc_var + 1;
     if mc_var = 10000000 then
          mc_var <= others => '0');
     end if;
END IF;
end process;

Does this function the same as using reset in the sensitivity?

Upvotes: 0

Views: 118

Answers (2)

mkrieger1
mkrieger1

Reputation: 23235

Plus: these initial values can be honored by logic synthesizers only on hardware targets that support power-on initializations (namely FPGAs). On ASIC-like targets they are frequently ignored.

This was originally posted by Renauld Pacalet as a comment to this answer.

Upvotes: 0

mkrieger1
mkrieger1

Reputation: 23235

No, initializing a value is not the same as providing a reset option.

A reset input allows to reset the circuit to a defined state after it has started running.

An initial value only sets the circuit to a defined state at the beginning, but then it can't be reset.

Upvotes: 3

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