Reputation: 251
Arm A72 core TRM specifies that L1 has a 'fill buffer' and that L2 has a 'fill/evict queue' and the manual does not mention anywhere what they do. Am I right in assuming the following
Upvotes: 0
Views: 367
Reputation: 364009
Probably a "fill buffer" is something that waits for / tracks the incoming cache line between sending out a request and the data coming back. Loads from that cache line can attach themselves to it, so they get notified when data comes back (so it can get written to registers and, if needed, forwarded to instructions waiting to read those registers).
That's what Line Fill Buffers do in Intel CPUs. (Although in Intel CPUs, LFBs are used for stores as well.)
Upvotes: 0