CODEWITHSUNDEEP
synchronizationsystem-verilogspecman
user3697021
user3697021

Reputation: 13

SystemVerilog equivalent for specman's sys.tick_end

I have a System Verilog code that does checking based on a reference model. The ref model is updated by several analysis ports (in a monitor) in parallel, and also being read by my checker.

The shared ref model holds many data objects and the checker needs to "look" on multiple objects at the same cycle.

I need to somehow sync my checker to wait until all transactions from current cycle on the monitor's analysis ports will update the ref model. However, it is not guaranteed which task executes first : monitor's tasks or my checker tasks, so my checker may read stale (not updated) value from the reference model.

When I used to work with Specman, such issues could have been solved by using sys.tick_end() at the checker. This guaranteed that checker code will execute "at the end of the current cycle" - after all ports monitors already updated the reference model.

Is there any SystemVerilog equivalent for Specman's sys.tick_end() ?

Alternatively, is there any other method to sync a checker to wait until "all monitors did their updates for current cycle" ?

Thanks, Roi.

Upvotes: 1

Views: 106

Answers (1)

dave_59
dave_59

Reputation: 42738

From the way you worded your question, it appears you might be using the UVM. If that is correct, the UVM has a method uvm_wait_for_nba_region() which under most circumstances gives you the behavior you are looking for. This assumes all the analysis ports are synchronized to the same clock. It effectively makes them behave like they were assigned using a non-blocking assignment—eliminating any race conditions.

Upvotes: 2

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