CODEWITHSUNDEEP
synchronizationwaitsystem-verilogspecman
Mondy Garcia
Mondy Garcia

Reputation: 11

System Verilog Counterpart for 'sync' of Specman e

I would like to ask what is the counterpart of sync of Specman e in the System Verilog Language.

I understand that @ event_indentifier is equivalent to wait @ event of Specman e. But how about sync @ event ?

Upvotes: 1

Views: 2080

Answers (2)

jclin
jclin

Reputation: 2579

Part of 13.1.1 of IEEE 1647 says

The sync action is similar to the wait action, except that a wait action always requires at least one cycle of the TCM’s sampling event before execution can continue. With a sync action, execution can continue in the same time step.

Part of draft of 1647-2008

For sync

When an TCM reaches a sync action, its execution shall be suspended so some other TCM, or the suspended TCM itself, can be scheduled for execution.

For wait

When a TCM reaches a wait action, its execution shall be suspended so some other TCM can be scheduled for execution. The suspended TCM itself shall remain idle and shall not be scheduled until the next occurrence of the sampling event.

I think you are comparing the different things. SystemVerilog is the simulation engine and kernel, and Specman is like a add-on or plugin on to the kernel to monitor and check something you wrote in e language. In SystemVerilog the event is for its simulation events, and Specman also creates it own events for its TCM processes. So in Specman, it has its own TCM process scheduling. If you use sync, it could make the synchronization without extra cycle; use wait and cause at least one cycle for the sampling cycle. Of course, if sync and wait does not have the temporal expression, they both use the TCM default sampling events and could have one or more cycles.

SystemVerilog is also event-based simulator. It does have delta cycles in each time step. You can download IEEE 1800-2012 SystemVerilog LRM in http://standards.ieee.org/getieee/1800/download/1800-2012.pdf, and see 4.5 for its scheduling reference algorithm. But in the Hardware modeling, it has no explicitly wait synx for zero cycle delay in the current simulation time step because the simulator will automatically schedule the process with sensitivity list to be run. If you have to compare Specman with SystemVerilog, it should be specifically SystemVerilog Assertion syntax. There is ##0 syntax in SVA to cause the assertion process to have zero cycle delay before next assertion expressions.

Upvotes: 1

dwikle
dwikle

Reputation: 6978

For named events, you can use the triggered property.

event ev;
...
wait (ev.triggered);

See chapter 15.5.3 of the the 2012 SystemVerilog LRM for a full explanation.

Upvotes: 1

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