CODEWITHSUNDEEP
system-verilog-assertions
Charmi Toliya
Charmi Toliya

Reputation: 11

Assertion writing without clock for async reset

I have two resets in my design. Reset_a and Reset_b. both are asynchronous reset can come at any pint of time. i have to write assertion to check if Reset_a is asserted Reset_b also assert at any point. We don't have clock enable in this case.

can anyone help how to write assertion?

I have tried below code.

reset_assertion_check:
    assert property (@(posedge reset_a) $rose(reset_b) ##[*0:$] reset_b)
    else
      $error("reset error");

Upvotes: -2

Views: 879

Answers (1)

Fengyi Jin
Fengyi Jin

Reputation: 76

create dummy clock(any period) on test bench, then use the dummy clock to check Reset_a and Reset_b use assertion.

Upvotes: 0

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